[Armv8] HCR_EL2 레지스터의 비트 맵

https://github.com/xen-project/xen/blob/stable-4.15/xen/arch/arm/p2m.c

setup_virt_paging_one() 함수 구현부 

static void setup_virt_paging_one(void *data)

{

    WRITE_SYSREG32(vtcr, VTCR_EL2);

    /*

     * ARM64_WORKAROUND_AT_SPECULATE: We want to keep the TLBs free from

     * entries related to EL1/EL0 translation regime until a guest vCPU

     * is running. For that, we need to set-up VTTBR to point to an empty

     * page-table and turn on stage-2 translation. The TLB entries

     * associated with EL1/EL0 translation regime will also be flushed in case

     * an AT instruction was speculated before hand.

     */

    if ( cpus_have_cap(ARM64_WORKAROUND_AT_SPECULATE) )

    {

        WRITE_SYSREG64(generate_vttbr(INVALID_VMID, empty_root_mfn), VTTBR_EL2);

        WRITE_SYSREG(READ_SYSREG(HCR_EL2) | HCR_VM, HCR_EL2);

        isb();

        flush_all_guests_tlb_local();

    }

}

HCR_EL2 레지스터에 HCR_VM를 설정 

HCR_VM의 정체는?

0000000000258518 <setup_virt_paging_one>:

  258518: f00001c0 adrp x0, 293000 <key_table+0x780>

  25851c: 912d0001 add x1, x0, #0xb40

...

  25853c: d51c2100 msr vttbr_el2, x0

  258540: d53c1100 mrs x0, hcr_el2

  258544: b2400000 orr x0, x0, #0x1

  258548: d51c1100 msr hcr_el2, x0

HCR_VM은 0x1임 

https://github.com/xen-project/xen/blob/stable-4.15/xen/include/asm-arm/processor.h

/* HCR Hyp Configuration Register */

#define HCR_RW          (_AC(1,UL)<<31) /* Register Width, ARM64 only */

#define HCR_TGE         (_AC(1,UL)<<27) /* Trap General Exceptions */

#define HCR_TVM         (_AC(1,UL)<<26) /* Trap Virtual Memory Controls */

#define HCR_TTLB        (_AC(1,UL)<<25) /* Trap TLB Maintenance Operations */

#define HCR_TPU         (_AC(1,UL)<<24) /* Trap Cache Maintenance Operations to PoU */

#define HCR_TPC         (_AC(1,UL)<<23) /* Trap Cache Maintenance Operations to PoC */

#define HCR_TSW         (_AC(1,UL)<<22) /* Trap Set/Way Cache Maintenance Operations */

#define HCR_TAC         (_AC(1,UL)<<21) /* Trap ACTLR Accesses */

#define HCR_TIDCP       (_AC(1,UL)<<20) /* Trap lockdown */

#define HCR_TSC         (_AC(1,UL)<<19) /* Trap SMC instruction */

#define HCR_TID3        (_AC(1,UL)<<18) /* Trap ID Register Group 3 */

#define HCR_TID2        (_AC(1,UL)<<17) /* Trap ID Register Group 2 */

#define HCR_TID1        (_AC(1,UL)<<16) /* Trap ID Register Group 1 */

#define HCR_TID0        (_AC(1,UL)<<15) /* Trap ID Register Group 0 */

#define HCR_TWE         (_AC(1,UL)<<14) /* Trap WFE instruction */

#define HCR_TWI         (_AC(1,UL)<<13) /* Trap WFI instruction */

#define HCR_DC          (_AC(1,UL)<<12) /* Default cacheable */

#define HCR_BSU_MASK    (_AC(3,UL)<<10) /* Barrier Shareability Upgrade */

#define HCR_BSU_NONE     (_AC(0,UL)<<10)

#define HCR_BSU_INNER    (_AC(1,UL)<<10)

#define HCR_BSU_OUTER    (_AC(2,UL)<<10)

#define HCR_BSU_FULL     (_AC(3,UL)<<10)

#define HCR_FB          (_AC(1,UL)<<9) /* Force Broadcast of Cache/BP/TLB operations */

#define HCR_VA          (_AC(1,UL)<<8) /* Virtual Asynchronous Abort */

#define HCR_VI          (_AC(1,UL)<<7) /* Virtual IRQ */

#define HCR_VF          (_AC(1,UL)<<6) /* Virtual FIQ */

#define HCR_AMO         (_AC(1,UL)<<5) /* Override CPSR.A */

#define HCR_IMO         (_AC(1,UL)<<4) /* Override CPSR.I */

#define HCR_FMO         (_AC(1,UL)<<3) /* Override CPSR.F */

#define HCR_PTW         (_AC(1,UL)<<2) /* Protected Walk */

#define HCR_SWIO        (_AC(1,UL)<<1) /* Set/Way Invalidation Override */

#define HCR_VM          (_AC(1,UL)<<0) /* Virtual MMU Enable */

EL1에서 실행되는 게스트 OS에서 설정된 인터럽트가 발생하면 일반적으로 EL1에서 받아 처리합니다.

만약 HCR_EL2 레지스터의 VI와 IMO 비트가 1로 설정된 경우에만, EL2가 EL1에서 설정된 인터럽트를 받게 됩니다.